1樓：哈哈呵呵你好
你好，下面是對應的邏輯：ctrl0控制速度，ctrl1控制方向module walkled_8(led,clk，ctrl);
input clk;
input [1:0] ctrl;
output [7:0] led;
reg [7:0] led_out, vv;
reg [25:0] buffer;
assign changev = (ctrl[0:0] ==1)? 26』d50000000 : 26』d25000000;
always@(posedge clk)
begin
buffer<=buffer+1'b1;
if(buffer==changev)
begin
if (ctrl[1:1]==0) beginled_out = led_out<<1;
vv = 8』h1; end
else begin
led_out = led_out>>1;
vv = 8』h80;
if(led_out==8'b00000000)led_out=vv;
endbuffer = 1;
endassign led=led_out;
endmodule
急求控制方向的跑馬燈verilog程式設計！！！！！！！ 5
2樓：匿名使用者
module paomadeng(
input clk,
input rst_n,
input direction,output reg [7:0] deng);integer i;
reg on_off;
always @(posedge clk or negedge rst_n) begin
if(rst_n==1'b0)
on_off<= 8'b0;
on_off <= ~on_off;
endalways @(posedge clk or negedge rst_n) begin
if(rst_n==1'b0)
deng <= 8'b0;
else begin
case(direction)
0:begin
deng[0] <= on_off;
for (i=0;i<7;i++)
deng[i+1]<=deng[i];
end1:begin
deng[7] <= on_off;
for (i=7;i>0;i++)
deng[i-1]<=deng[i];
endendcase
endend
endmodule
右跑為例，依次如下
00000000
10000000
11000000
11100000
。。。11111111
01111111
00111111
00011111
。。。00000000
direction接開關，deng接8位led燈
3樓：漢語拼音
這個簡單，你設一個暫存器reg型別的那種，然後控制他的值，把想亮的那位設定成1，其他位設定成0，然後每個時鐘移動一次。。如果是共陽的led，就是0是亮的，1是暗的。
用verilog hdl設計一個完整的分頻器模組，實現100mhz分頻為500hz，方式不限。
4樓：匿名使用者
100mhz就是1億，分頻到500，就是1億/500=20萬，只需要時序計數，逢20萬一個週期即可，即10萬一次訊號翻轉
設計一個控制系統並**，怎麼實現跑馬燈速度變化啊？求大佬程式設計。
5樓：匿名使用者
網上找出單獨的程式，自己組合除錯到一起，先編不是很快就可完成的，拿來主義看看誰閒著沒事會給你寫吧！
6樓：匿名使用者
不知道。。。。。。。。。。。。。。
7樓：陽光的凌寶寶
再去對應類的作用域，依然未找到
用verilog hdl語言編寫跑馬燈之中間兩個燈向兩邊亮,再從兩邊向中間亮
8樓：匿名使用者
module top(
clk_in,
led0,
led1,
led2,
led3,
led4,
led5,
led6,
led7
);input clk_in;
output led0;
output led1;
output led2;
output led3;
output led4;
output led5;
output led6;
output led7;
reg led0;
reg led1;
reg led2;
reg led3;
reg led4;
reg led5;
reg led6;
reg led7;
reg [25:0]cnt;
reg [5:0]state;
wire clk;
wire rst;
pll pll(
.clkin (clk_in),
.clkout0(clk),//100m
.locked (rst)
);always @(posedge clk or negedge rst ) begin
if(!rst)
cnt<=0;
else if (cnt[25]) begincnt<=0;
endelse
begin
cnt<=cnt+26'd1;
endend
always @(posedge clk or negedge rst) begin
if(!rst)begin
led0<=1;
led1<=1;
led2<=1;
led3<=1;
led4<=1;
led5<=1;
led6<=1;
led7<=1;
state<=0;
endelse begin
case (state)
0:begin
if (cnt[25]) begin
state<=1;
led0<=1;
endelse begin
state<=state;
led0<=0;
endend
1: begin
if (cnt[25]) begin
state<=2;
led1<=1;
endelse begin
state<=state;
led1<=0;
endend
2: begin
if (cnt[25]) begin
state<=3;
led2<=1;
endelse begin
state<=state;
led2<=0;
endend
3: begin
if (cnt[25]) begin
state<=4;
led3<=1;
endelse begin
state<=state;
led3<=0;
endend
4: begin
if (cnt[25]) begin
state<=5;
led4<=1;
endelse begin
state<=state;
led4<=0;
endend
5: begin
if (cnt[25]) begin
state<=6;
led5<=1;
endelse begin
state<=state;
led5<=0;
endend
6: begin
if (cnt[25]) begin
state<=7;
led6<=1;
endelse begin
state<=state;
led6<=0;
endend
7: begin
if (cnt[25]) begin
state<=8;
led7<=1;
endelse begin
state<=state;
led7<=0;
endend
8: begin
if (cnt[25]) begin
state<=9;
led6<=1;
endelse begin
state<=state;
led6<=0;
endend
9: begin
if (cnt[25]) begin
state<=10;
led5<=1;
endelse begin
state<=state;
led5<=0;
endend
10: begin
if (cnt[25]) begin
state<=12;
led4<=1;
endelse begin
state<=state;
led4<=0;
endend
12: begin
if (cnt[25]) begin
state<=13;
led3<=1;
endelse begin
state<=state;
led3<=0;
endend
13: begin
if (cnt[25]) begin
state<=14;
led2<=1;
endelse begin
state<=state;
led2<=0;
endend
14: begin
if (cnt[25]) begin
state<=15;
led1<=1;
endelse begin
state<=state;
led1<=0;
endend
15: begin
if (cnt[25]) begin
state<=16;
led0<=1;
led7<=1;
endelse begin
state<=state;
led0<=0;
led7<=0;
endend
16: begin
if (cnt[25]) begin
state<=17;
led1<=1;
led6<=1;
endelse begin
state<=state;
led1<=0;
led6<=0;
endend
17: begin
if (cnt[25]) begin
state<=18;
led2<=1;
led5<=1;
endelse begin
state<=state;
led2<=0;
led5<=0;
endend
18: begin
if (cnt[25]) begin
state<=19;
led3<=1;
led4<=1;
endelse begin
state<=state;
led3<=0;
led4<=0;
endend
19: begin
if (cnt[25]) begin
state<=20;
led2<=1;
led5<=1;
endelse begin
state<=state;
led2<=0;
led5<=0;
endend
20: begin
if (cnt[25]) begin
state<=21;
led1<=1;
led6<=1;
endelse begin
state<=state;
led1<=0;
led6<=0;
endend
21: begin
if (cnt[25]) begin
state<=0;
led0<=1;
led7<=1;
endelse begin
state<=state;
led0<=0;
led7<=0;
endend
default:begin
state<=0;
endendcase
endend
endmodule
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